Test generation for E-beam testing of VLSI circuits

With the increasing use of E-beam testing, chip test under highly observable condition has become increasing important. Using E-beam probing, the logical value of the internal signal lines running in the top-metal layer can be observed directly. The number of test vectors can be reduced by observing internal nodes. In this paper, we access a method to generate test vectors and corresponding internal nodes for single stuck-at faults in combinational circuits. This approach differs from the conventional methods which generates test vectors with a fixed number of observable points