DocumentCode
2671757
Title
Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process
Author
Chiu, Po-Yen ; Ker, Ming-Dou ; Tsai, Fu-Yi ; Chang, Yeong-Jar
Author_Institution
Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
fYear
2009
fDate
26-30 April 2009
Firstpage
750
Lastpage
753
Abstract
A new power-rail ESD clamp circuit with ultra-low-leakage design is presented and verified in a 65-nm CMOS process with a leakage current of only 116 nA at 25degC, which is much smaller than that (613 muA) of traditional design. Moreover, it can achieve ESD robustness of over 8 kV in HBM and 800 V in MM ESD tests, respectively.
Keywords
CMOS integrated circuits; electrostatic discharge; low-power electronics; current 116 nA; electrostatic discharge; leakage current; nanoscale low-voltage CMOS process; size 65 nm; temperature 25 degC; ultra-low-leakage power-rail ESD clamp circuit; voltage 8 kV; voltage 800 V; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; Gate leakage; Leak detection; Leakage current; MOS capacitors; Thyristors; ESD clamp circuit; electrostatic discharge (ESD); gate leakage; silicon-controlled rectifier (SCR);
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2009 IEEE International
Conference_Location
Montreal, QC
ISSN
1541-7026
Print_ISBN
978-1-4244-2888-5
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2009.5173343
Filename
5173343
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