A 15-valued fast test generation for combinational circuits

This paper proposes a test generation algorithm which can be applied to practical VLSI circuits. The key idea of the algorithm is to construct a sensitized path from the primary output to the site of the fault. This change of path construction order is very effective especially for the redundant faults, where their fault effects never propagate to any primary output. Whether or not a fault effect propagates can be easily checked by using 15-value logic. In this case, we can save computation time by not processing path sensitization. Another advantage of this approach is that the number of backtracks is greatly reduced by using information on the fault propagation during the path sensitization and line justification processes. This algorithm is implemented in C and is tested with the well-known benchmark circuits. The test results show that the new algorithm is extremely faster than PODEM