Title :
A heuristic for decomposition in multi-level logic optimization
Author :
Singh, Vinaya Kumar ; Diwan, A.A.
Author_Institution :
ASIC Technologies Pvt. Ltd.
Keywords :
Boolean functions; Computer networks; Costs; Logic; Network synthesis;
Conference_Titel :
VLSI Design, 1993. Proceedings. The Sixth International Conference on
Print_ISBN :
0-8186-3180-5
DOI :
10.1109/ICVD.1993.669622
