Dual-gate SOI CMOS technology by local overgrowth (LOG)

Author

Zingg, R.P. ; Hofflinger, B. ; Neudeck, G.W.

Author_Institution

Inst. for Microelectron., Stuttgart, West Germany

fYear

1989

fDate

3-5 Oct 1989

Firstpage

134

Lastpage

135

Abstract

Summary form only given. A dual-gate CMOS process with excellent device performance is discussed. The low parasitics of SOI devices can be obtained without the penalty of degraded channel mobility that is often observed in zone melting recrystallized (ZMR) material. Low mask count, reduced diffusion times compared to bulk CMOS processing, and excellent planarity enable further stacking or multilayer metallization. Interconnect complexity is greatly simplified by vertical vias to the substrate, providing one power bus. The process gets simpler as device dimensions are scaled down

Keywords

CMOS integrated circuits; integrated circuit technology; semiconductor epitaxial layers; semiconductor growth; semiconductor-insulator boundaries; LOG; SOI CMOS technology; SOI devices; channel mobility; device dimensions; dual-gate CMOS process; excellent planarity; further stacking; local overgrowth; low mask count; low parasitics; multilayer metallization; process simplification; reduced diffusion times; scaling; vertical vias; CMOS technology; Circuits; Crystallization; Epitaxial growth; Plasma applications; Plasma chemistry; Silicon on insulator technology; Substrates; Transconductance; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

SOS/SOI Technology Conference, 1989., 1989 IEEE

Conference_Location

Stateline, NV

Type

conf

DOI

10.1109/SOI.1989.69802

Filename

69802