LFSROM: A hardware test pattern generator for deterministic ISCAS85 test sets

Deterministic testing is by far the most interesting built-in self-test (BIST) technique because of the minimal number of test patterns required and of the known fault coverage. However, it is still not applicable since none of the existing deterministic test pattern generators (TPGs) is at the same time efficient and small. The LFSROM architecture which is presented herein is thus an attempt to solve the hardware cost problem without altering the initial test sequence in order to preserve the advantages of minimal sequence length of deterministic testing over pseudo-random and (pseudo)-exhaustive testing. The LFSROM concept is described and several implementations of test sets generated for the ISCAS85 benchmark circuits have been compared with those of equivalent ROM designs and the results reported in the form of curves and bar charts