Title :
Additive cellular automata as an on-chip test pattern generator
Author :
Nandi, S. ; Chaudhuri, P. Pal
Author_Institution :
Dept. of Comput. Sci. & Engg., Indian Inst. of Technol., Kharagpur, India
Abstract :
Cellular Automata (CA) has been already proposed for generation of pseudo-random, pseudo-exhaustive and two-pattern test vectors. In the present work, a new concept of intermediate boundary CA has been projected that circumvents the problems associated with the generation of pseudo-random patterns using null and periodic boundary CA. Generation of an arbitrary set of deterministic test patterns for combinational logic is next investigated. Evaluating the given pattern set as a pseudo-noise (PN) sequence, a CA can be identified that generates the pattern set with minimal overhead. The best possible CA is picked up based on the analytical study of phaseshift analysis of various CA stages. Experimental results establishes this scheme as the desirable alternative to the conventional `store and generate´ schemes
Keywords :
automatic testing; built-in self test; cellular automata; combinational circuits; integrated circuit testing; integrated logic circuits; logic testing; polynomials; BIST; additive cellular automata; combinational logic; intermediate boundary CA; on-chip test pattern generator; periodic boundary CA; phaseshift analysis; primitive polynomial; pseudo-noise sequence; pseudo-random patterns; psuedo-exhaustive sequence; two-pattern test vectors; Automatic testing; Built-in self-test; Circuit testing; Clocks; Computer science; Hardware; Logic testing; Polynomials; Test pattern generators; Very large scale integration;
Conference_Titel :
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location :
Beijing
Print_ISBN :
0-8186-3930-X
DOI :
10.1109/ATS.1993.398797
