Title :
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC
Author :
Sülflow, André ; Drechsler, Rolf
Author_Institution :
Inst. of Comput. Sci., Univ. of Bremen, Bremen
Abstract :
In this paper we describe how to model arithmetic circuits over GF(pm) in SystemC. An extension of a GF(2m) multiplier is presented to support GF(pm) arithmetic as well. A full integration in the simulation environment is discussed and the proposed solution can be fully synthesized down to hardware. This finds application in e.g. cryptographic systems. As a case study a Reed-Solomon encoder/decoder system was developed with full GF(pm) encoding/decoding capability. It is shown that the modeling of a HW/SW co-design system in SystemC can improve the speed of simulation by a factor of up to 17.
Keywords :
Reed-Solomon codes; cryptography; hardware description languages; hardware-software codesign; multiplying circuits; GF arithmetic; GF multiplier; HW/SW co-design system; Reed-Solomon decoder; Reed-Solomon encoder; SystemC; arithmetic circuits; cryptographic systems; Circuits; Computer science; Decoding; Digital arithmetic; Encoding; Error correction; Galois fields; Hardware; Polynomials; Reed-Solomon codes;
Conference_Titel :
Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on
Conference_Location :
Oslo
Print_ISBN :
0-7695-2831-7
DOI :
10.1109/ISMVL.2007.34