DocumentCode
2671964
Title
Multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths
Author
Takahashi, Hiroshi ; Yanagida, Nobuhiro ; Takamatsu, Yuzo
Author_Institution
Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
fYear
1993
fDate
16-18 Nov 1993
Firstpage
185
Lastpage
190
Abstract
We describe a method for multiple stuck-at fault diagnosis in combinational circuits based on restricted single sensitized paths generated by a seven-valued calculus. Our method determines the set of all possible stuck-at faults from the faulty response observed at the primary output, based on deducing internal values along the sensitized path. By using the fault-free response observed at the primary output, we remove fault-free lines along the sensitized path from the set of the candidates, by checking whether the fault-free response is prevented by the candidate fault from propagating to the primary output regardless of the presence of any other candidates. Experimental results on the benchmark circuits show that the fault locations are identified within 2-25% of all stuck-at 0 and 1 faults on all lines in the circuit with up to fourfold multiple faults without probing internal lines
Keywords
VLSI; combinational circuits; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; VLSI; benchmark circuits; combinational circuits; fault-free lines; fourfold multiple faults; internal values; multiple stuck-at fault diagnosis; restricted single sensitized paths; seven-valued calculus; Algorithm design and analysis; Cause effect analysis; Circuit analysis computing; Circuit faults; Circuit testing; Combinational circuits; Computer science; Fault diagnosis; Fault location; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location
Beijing
Print_ISBN
0-8186-3930-X
Type
conf
DOI
10.1109/ATS.1993.398800
Filename
398800
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