Title :
A C-testable DCVS GF(2m) multiplier
Author :
Chang, Tsin-Yuan ; Chen, Ju-Hung ; Hsu, Jain-Bean
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
A C-testable design, which requires only five test patterns, for dynamic clocked differential cascode voltage switch (DCVS) GF(2m ) multiplier circuit is proposed. The hardware overhead includes two extra control lines and m XOR gates. For simplicity, the area overhead in transistor counts is 13m+1 for a GF(2 m) multiplier
Keywords :
design for testability; fault diagnosis; logic testing; multiplying circuits; XOR gates; area overhead; design for testability; dynamic clocked differential cascode voltage switch; fault diagnosis; hardware overhead; logic testing; multiplier circuit; transistor counts; Circuit faults; Circuit testing; Clocks; Electrical fault detection; Fault detection; Hardware; Monitoring; Switches; Switching circuits; Voltage;
Conference_Titel :
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location :
Beijing
Print_ISBN :
0-8186-3930-X
DOI :
10.1109/ATS.1993.398805
