Testing scheduling and control in a parallel processing environment

Author

Dong, Xiang

Author_Institution

Inst. of Comput. Technol., Academia Sinica, Beijing, China

fYear

1993

fDate

16-18 Nov 1993

Firstpage

262

Lastpage

267

Abstract

In this paper, the testing scheduling problem based on circuit partitioning is formulated into index coloring of the parallel testing graph (PTG). It is known that the index coloring problem is exponential in time cost, but the testing scheduling problem is proved to be polynomially solvable in theory. According to this result, an optimal testing scheduling algorithm is offered in quadratic time. Finally, a control scheme during testing scheduling is presented, which minimizes the number of the extra control inputs of the multiplexors to 2.1n ICN, here ICN is the index chromatic number of the PTG

Keywords

automatic testing; graph colouring; graph theory; logic partitioning; logic testing; optimisation; parallel algorithms; polynomials; scheduling; VLSI; circuit partitioning; control; index chromatic number; index coloring; multiplexors; optimal testing scheduling algorithm; parallel processing environment; parallel testing graph; polynomial; quadratic time; time cost; Circuit faults; Circuit simulation; Circuit testing; Computers; Costs; Optimal control; Parallel processing; Processor scheduling; Scheduling algorithm; Sequential analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1993., Proceedings of the Second Asian

Conference_Location

Beijing

Print_ISBN

0-8186-3930-X

Type

conf

DOI

10.1109/ATS.1993.398815

Filename

398815