General design principles of self-testing code-disjoint PLAs

Author

Piestrak, Stanislaw J.

Author_Institution

Inst. of Eng. Cybernetics, Tech. Univ. of Wroclaw, Poland

fYear

1993

fDate

16-18 Nov 1993

Firstpage

287

Lastpage

292

Abstract

This paper presents general principles of designing self-testing (ST) code-disjoint (CD) PLAs under fault model which covers three classes of typical PLA faults. It is assumed that both inputs and outputs of a PLA are encoded with an unordered code and that PLAs are inverter-free. It is shown that the necessary condition for ST and CD is that the input code of a PLA is closed. The formal conditions for the existence of a one- and multi-stage ST and CD PLA are formulated. The new PLA-based self-testing checkers for various closed unordered codes are less complex and/or faster than existing designs, and for some unordered codes they are the first ever proposed. An important property of all new designs is that they are all single crosspoint irredundant

Keywords

automatic testing; design for testability; fault diagnosis; logic design; logic testing; programmable logic arrays; PLA; closed unordered codes; code disjoint PLA; fault model; multistage self-testing; necessary condition; single crosspoint irredundant design; unordered code; Built-in self-test; Circuit faults; Costs; Cybernetics; Electronic mail; Fault diagnosis; Programmable logic arrays; Protection; Read only memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1993., Proceedings of the Second Asian

Conference_Location

Beijing

Print_ISBN

0-8186-3930-X

Type

conf

DOI

10.1109/ATS.1993.398819

Filename

398819