Frequency and recovery effects in high-κ BTI degradation

Author

Ramey, Stephen ; Prasad, Chetan ; Agostinelli, Marty ; Pae, Sangwoo ; Walstra, Steven ; Gupta, Satrajit ; Hicks, Jeffrey

Author_Institution

Logic & Technol. Dev. Quality & Reliability, Intel Corp., Hillsboro, OR, USA

fYear

2009

fDate

26-30 April 2009

Firstpage

1023

Lastpage

1027

Abstract

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-kappa recovery behavior observed is consistent with SiO₂ gate stacks, which allows the use of SiO₂ models to predict recovery in both NMOS and PMOS high-kappa transistors.

Keywords

MOSFET; high-k dielectric thin films; life testing; semiconductor device models; semiconductor device reliability; silicon compounds; NMOS transistors; PMOS transistors; SiO₂; bias-temperature instability; end-of-life aging prediction; gate stacks; high-kappa BTI degradation; high-kappa recovery behavior; net degradation model; product aging model; Aging; CMOS logic circuits; Degradation; Frequency; Inverters; MOS devices; MOSFETs; Predictive models; Stress measurement; Voltage; Bias-Temperature Instability; Hi-κ; Recovery; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2009 IEEE International

Conference_Location

Montreal, QC

ISSN

1541-7026

Print_ISBN

978-1-4244-2888-5

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2009.5173404

Filename

5173404