DocumentCode :
2672778
Title :
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits
Author :
Parekhji, R.A. ; Venkatesh, G. ; Sherlekar, S.D.
Author_Institution :
Indian Institute of Technology
fYear :
1993
fDate :
3-6 Jan 1993
Firstpage :
15
Lastpage :
20
Keywords :
Circuit faults; Clocks; Computerized monitoring; Condition monitoring; Cost function; Delay; Design methodology; Electrical fault detection; Hypercubes; Sequential circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1993. Proceedings. The Sixth International Conference on
ISSN :
1063-9667
Print_ISBN :
0-8186-3180-5
Type :
conf
DOI :
10.1109/ICVD.1993.669627
Filename :
669627
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2672778
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