Design of a novel low power 6-T CNFET SRAM cell working in sub-threshold region

A novel low power 6-T SRAM cell operating in sub-threshold region based on CNFET is presented. Compared with the 4-T SRAM structure, the proposed 6-T SRAM structure can operate with 0.4 V supply voltage, which is not possible for the 4-T structure. The proposed 6-T SRAM structure is optimized with the back-gate biasing technique for speed and stability improvements. Compared with a conventional 6-T cell, simulation results show that the read and write delay have been improved by more than 80% and 75% at 0.4 V supply voltage, respectively. The proposed 6-T SRAM cell achieves power reduction of 33.3% and 59.6% for read and write operations, respectively compared with the traditional 6-T SRAM cell while the supply voltage is at 0.4 V. The read and write PDP are 70% and 91% smaller than that of 6-T cell.