Ultralow power SRAM design in near threshold region using 45nm CMOS technology

Subthreshold leakage, dynamic power consumption and delay are major issues for circuits design, especially for SRAM design. Subthreshold leakage and dynamic power consumption can be decreased while supply voltage is scaled down. However, this may dramatically increase the circuit delay. In this paper, we proposed a novel 6t SRAM design which operates in near threshold region to optimize leakage power and speed. In this paper, negative word line is introduced to reduce the leakage current. A novel Latch-type voltage sense amplifier is proposed to improve the read speed of the proposed SRAM cell. The proposed SRAM design is implemented in 45nm technology and achieves more than 50% for power reduction, 68% for leakage reduction, 90% for write delay reduction and 78% for read delay reduction compared to traditional 6T SRAM in near threshold region.