Energy reductions for embedded processors in reconfigurable hardware

The use of reconfigurable hardware in embedded applications is steadily growing as industry´s need for flexible systems with reduced component count rises. As each generation passes, the size of embedded system components is shrinking and the primary energy concern is shifting from dynamic power to static power consumption. With processes moving towards 45 nm and smaller, subthreshold current leakage and gate oxide leakage are accounting for a larger percentage of energy consumption, often overtaking that of dynamic power. As processes continue to shrink, static power will continue to grow to unacceptable levels rendering most reconfigurable hardware incapable of competing in mobile market solutions. In this paper we examine two methods of reducing the static power consumption to lessen the energy consumption of a Xilinx Spartan 3E Field Programmable Gate Array (FPGA). In order to examine the effects of each method, two processors differing in complexity and size were created and simulated single precision floating point addition and multiplication operations were executed on them. The two methods employed results in an average of more than 70% static power savings for a very simple processor as well as more than 40% static power savings for a Relatively Simple processor.