Title :
Heuristics for the placement of flip-flops in partial scan designs and the placement of signal boosters in lossy circuits
Author :
Paik, Doowon ; Reddy, Sudhakar ; Sahni, Sartaj
Author_Institution :
AT&,T Bell Labs
Keywords :
Circuits; Delay; Flip-flops; Latches; Signal design; Terminology; Tree graphs;
Conference_Titel :
VLSI Design, 1993. Proceedings. The Sixth International Conference on
Print_ISBN :
0-8186-3180-5
DOI :
10.1109/ICVD.1993.669636
