Evaluation of fault-tolerant designs implemented on SRAM-based FPGAs

Author

Asadi, Ghazanfar ; Miremadi, Seyed Ghassem ; Zarandi, Hamid R. ; Ejlali, Alireza

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2004

fDate

3-5 March 2004

Firstpage

327

Lastpage

332

Abstract

The technology of SRAM-based devices is sensible to single event upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. We present a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC´99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device.

Keywords

SRAM chips; benchmark testing; fault tolerant computing; field programmable gate arrays; Altera FPGA; SRAM-based FPGA; configuration bitstream file; fault-tolerant designs; field programmable gate arrays; single event upsets; Aerospace electronics; Application software; Application specific integrated circuits; Costs; Fault tolerance; Field programmable gate arrays; Logic devices; Prototypes; Single event transient; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

Dependable Computing, 2004. Proceedings. 10th IEEE Pacific Rim International Symposium on

Print_ISBN

0-7695-2076-6

Type

conf

DOI

10.1109/PRDC.2004.1276583

Filename

1276583