A 10 bit, 1.5b/stage pipeline ADC using a fully differential current conveyor with foreground calibration

The paper presents a 10 bit, 1.5b/stage fully differential pipeline ADC using a second generation current conveyor (CCII). The novelty lies in the use of passive common mode suppression to reject common mode signals and the use of CCII which as a replacement to opamps, provides good performance in applications where high bandwidth is needed. Additionally foreground calibration is used to correct errors due to interstage gain, offsets, charge injection, and changes in reference voltages. Simulation results show that the ADC works for differential inputs of (-500 mV, 500 mV) at 10 MHz sampling rate. The DNL and INL are within ±0.6 LSB and ±1.4 LSB respectively and the ENOB is 8.9 bits. The total power of the analog part is 8.1 mW in a 1 V/90 nm TSMC process.