The effect of placement on yield for standard cell designs

The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been developed. Yield improvement during routing is however, limited by the predetermined placement. It is conceivable therefore, that different placements of the modules (e.g., standard or custom cells) may lead to very different yield enhanced routings with different projected yields. This is conceptually similar to the effect that the floorplanning of the entire chip has on the yield, but while chip floorplanning deals with the major building blocks, placement deals with the modules within an individual block. Yield enhanced placement of modules has not been attempted before mainly due to the difficulty of estimating the yield of the block before the routing is done. Recently, a technique for estimating the yield prior to the routing has been developed making it possible to modify the placement in order to achieve higher yield. The goals of this paper are to investigate the effect that placement has on the projected yield and to modify a standard cell placement algorithm so that yield becomes a design objective