Predicting the yield efficacy of a defect-tolerant embedded core

The average new chip design already exceeds two million devices. Companies are racing to produce innovative systems-on-a-chip (SoC). Economic exigencies are mandating the re-use of core designs. These trends have led to new research concerns in SoC testing, SoC yield prediction, core interfacing, and intellectual property (IP) protection. In this work, we address design decisions associated with embedded cores that have defect-tolerant properties. Specifically, we address whether knowledge about the remainder of the chip would result in different core design decisions pertaining to yield