Title :
Quality-effective repair of multichip module systems
Author :
Park, N. ; Meyer, E. ; Lombardi, E.
Author_Institution :
Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
Abstract :
This paper proposes a new analytical approach for evaluating the effects of a repair process on the defect level of multichip module (MCM) systems at assembly. Repair of MCMs is usually required to improve the yield and quality of these systems, while preserving cost effectiveness. In the proposed approach, we develop a novel quality model, which is solved analytically in O(rN3) (where r is the maximum number of allowed repair cycles and N is the number of chips in the MCM). The proposed model is based on a previously proposed quality model for MCMs which did not incorporate the effect of a repair process on the defect level. The proposed model relates the defect level to various figures of merit of repair, such as the probability of successfully repairing a fault (referred to as repairability), the probability of damaging the system and the maximum allowed number of repair cycles. Parameteric results show that due to the repair process the overall defect-level decreases as the MCM yield increases; however, there exists a bound in the number of repair cycles, to permit an increase in repairability. Using these results, it is possible to predict a more accurate value of the defect level of MCMs by taking into account the different parameters affecting the repair process, while realistically reducing the defect level of the final MCM product
Keywords :
Markov processes; integrated circuit yield; multichip modules; probability; MCM systems; MCM yield; Markov model; cost effectiveness; defect level; maximum repair cycles number; multichip module systems; quality model; quality-effective repair; repair figures of merit; repairability; successfully repair probability; system damage probability; Assembly systems; Costs; Degradation; Fabrication; Integrated circuit packaging; Manufacturing; Multichip modules; Silicon; Testing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.886973