DocumentCode
2674870
Title
The implementation of high-speed FFT processor based on FPGA
Author
Xiao-Feng Li ; Long, Chen ; Shihu, Wang
Author_Institution
Dept. of Electromech. Eng., Beijing Inst. of Technol., Beijing, China
Volume
2
fYear
2010
fDate
24-26 Aug. 2010
Firstpage
236
Lastpage
239
Abstract
A method of implementing 256-point, high-speed and 16-bit complex FFT is presented on the radix-4 FFT algorithm. By using a fixed geometry addressing, pipeline designing and block floating point structure, the data has the greater precision and dynamic range. The results show that the design is efficient, strongly extensive and occupies less resource. It is a good method to meet the high-speed digital signal processing requirements.
Keywords
fast Fourier transforms; field programmable gate arrays; floating point arithmetic; microprocessor chips; pipeline arithmetic; FPGA; block floating point structure; fixed geometry addressing; high-speed FFT processor; high-speed digital signal processing requirements; pipeline designing; radix-4 FFT algorithm; Dairy products; block floating point; fixed geometry; high-speed FFT processor; pipeline;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer, Mechatronics, Control and Electronic Engineering (CMCE), 2010 International Conference on
Conference_Location
Changchun
Print_ISBN
978-1-4244-7957-3
Type
conf
DOI
10.1109/CMCE.2010.5609737
Filename
5609737
Link To Document