DocumentCode :
2674977
Title :
Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations
Author :
Hartmann, H.-D. ; Hillmann-Ruge, T.
Author_Institution :
Inst. fur Halbleitertechnol. und Werkstoffe der Elektrotech., Hannover Univ., West Germany
fYear :
1990
fDate :
23-25 Jan 1990
Firstpage :
298
Lastpage :
307
Abstract :
Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Ω has been achieved with expansions of 20×20 μm2. However, expansions of 14×14 μm2 are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1×106 A/cm2 and temperatures up to 270°C were carried out. Materials were analysed with EDX, AES, and SIMS
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; laser beam machining; laser beam welding; life testing; metallisation; solid lasers; 0.3 ohm; 14 micron; 20 micron; 270 C; AES; EDX; Nd:YAG laser processing; SIMS; WSI; YAG:Nd lasers; YAl5O12:Nd; antifuses; consumption of area; contact resistances; current densities; cutting of interconnections; expanded interconnections; laser formed connections; laser formed disconnections; laser linking; laser processing; life time tests; reliability; reproducibility; standard CMOS double level metallizations; standard double level CMOS process; temperatures; test chip; vertical links; yield; CMOS process; Joining processes; Laser beam cutting; Life estimation; Metallization; Optical pulses; Passivation; Reproducibility of results; Statistics; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-8186-9013-5
Type :
conf
DOI :
10.1109/ICWSI.1990.63913
Filename :
63913
Link To Document :
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