• DocumentCode
    2675072
  • Title

    Lowering the error floors of irregular high-rate LDPC codes by graph conditioning

  • Author

    Weng, Wen-Yen ; Ramamoorthy, Aditya ; Wesel, Richard D.

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • Volume
    4
  • fYear
    2004
  • fDate
    26-29 Sept. 2004
  • Firstpage
    2549
  • Abstract
    This paper applies a graph conditioning algorithm, called the approximate cycle extrinsic message degree (ACE) algorithm, to design high-rate (R≥1/2) irregular LDPC codes. The algorithm was shown to be an effective tool to lower the error floors of lower-rate (R≤1/2) LDPC codes. However, for high-rate LDPC codes, due to the large number of degree-2 variable nodes in the optimal degree distribution, the error floor is high and it is more difficult to condition the graph. By constraining the number of degree-2 nodes, we found that the ACE algorithm can dramatically lower the error floor with little compromise of the threshold. A rate-3/4, length-10688 LDPC code is proposed whose AWGN channel performance is within 0.67 dB of the Shannon limit at BER=10-5 and its error floor is lower than 10-7. Compared to existing semi-regular codes which lower the floor by adopting non-optimal degree distributions, our graph-conditioned codes provides 0.38 dB of performance improvement at BER=10-5. The same design criteria also apply well to medium-length LDPC code design and are suitable for rate-compatible applications using the information-ing technique. The rate-compatible scheme has consistently good thresholds and low error floors for 1/2≤ R≤ 8/9.
  • Keywords
    AWGN channels; error statistics; parity check codes; ACE algorithm; AWGN channel; BER; approximate cycle extrinsic message degree algorithm; code error floor lowering; degree-2 variable node constraints; graph conditioning; information-ing technique; irregular high-rate LDPC codes; medium-length LDPC code design; optimal degree distribution; rate-compatible codes; AWGN channels; Algorithm design and analysis; Bipartite graph; Bit error rate; Encoding; Floors; H infinity control; Matrix converters; Parity check codes; Sparse matrices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Vehicular Technology Conference, 2004. VTC2004-Fall. 2004 IEEE 60th
  • ISSN
    1090-3038
  • Print_ISBN
    0-7803-8521-7
  • Type

    conf

  • DOI
    10.1109/VETECF.2004.1400516
  • Filename
    1400516