Power-on reset circuit for SoC with multiple I/O power supplies

One significant requirement for portable devices implemented in System-on-a-Chip (SoC) technology is to perform safely under extreme voltage power supply scenarios. This paper presents an on-chip power-on reset (POR) circuit and an I/O power supply detection circuit, with low steady-state power consumption. The POR circuit evaluates both the digital core voltage supply (VDD) and the highest chip voltage supply (VCC), which can be either 2.5 V or 3.3 V. Our technique allows the I/O power supply monitoring to be performed independently from the core power supplies. The I/O power supply detection circuit has a fixed detection threshold and can detect both the rising and falling ramps of the supply voltage. The circuit can operate for any I/O supply voltage level ranging from 1.5 V to 3.3 V. Simulation results show very low steady state power consumption. As a result, the proposed POR circuit is suitable for low power applications and embedding in portable device systems.