A high speed and high fault tolerant reconfigurable reasoning system: toward a wafer scale reconfigurable reasoning LSI

A data direct implementation (DDI) technique for reasoning hardware using a large area FPGA or a wafer scale FPGA is proposed. In the DDI design methodology, the features in the past case data are extracted and converted to the truth tables using a genetic algorithm, and the truth tables (evolved truth tables) are synthesized to the logic circuits. Whereas the DDI requires reconfigurability in the circuits because the circuits are customized and updated in each reasoning task, it achieves high speed and high fault tolerant reasoning hardware because of the following reasons. Intrinsic high parallelism in the case data set as automatically embedded into the circuits and reasoning is derived from the whole of massively processed case data (some faulty circuits cannot affect the reasoning results). Thus, the DDI technique and the large area FPGA (or WSI-FPGA) seem to be an ideal marriage of new technologies. The DDI approach is applied to the English pronunciation reasoning (EPR) task and the EPR system, is implemented onto the newly developed FPGA-based reasoning board, which is regarded as a prototype of the WSI-FPGA. The EPR system achieves a high reasoning speed of 120 ns/phoneme and a high reasoning accuracy of 81.9% which is the same accuracy as neural networks and parallel AI. Furthermore, it obtains high fault tolerance showing no performance degradation even with 6% stuck-at faulty gate ratio