Fault-tolerant high-performance CORDIC processors

Author

Kwa, Jae-Hyuck ; Piuri, Vincenzo ; Swartzlander, Earl E., Jr.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

2000

fDate

2000

Firstpage

164

Lastpage

172

Abstract

This paper presents a low-cost approach to concurrent error detection in a high-performance CORDIC processor based on a conditional-sum scheme. The specific characteristics of the CORDIC computation and the processor allow fault detection at a low increase in circuit complexity and latency. The detection scheme is based on use of the AN codes for the arithmetic part and on duplication of the rotation direction generators. Granular-pipelining has been applied to provide a variety of different performance tradeoffs, all with the same fault detection capabilities

Keywords

VLSI; circuit complexity; digital arithmetic; digital signal processing chips; error detection; iterative methods; parallel architectures; pipeline arithmetic; AN codes; CORDIC processors; circuit complexity; concurrent error detection; conditional-sum; duplication; fault detection; granular-pipelining; iterative techniques; latency; rotation direction generators; Arithmetic; Complexity theory; Computer errors; Delay; Electrical fault detection; Fault tolerance; Hardware; Pipeline processing; Redundancy; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Conference_Location

Yamanashi

ISSN

1550-5774

Print_ISBN

0-7695-0719-0

Type

conf

DOI

10.1109/DFTVS.2000.887154

Filename

887154