Title :
RS encoder design based on FPGA
Author :
Xiaojun, Chang ; Jun, Guo ; Zhihui, Li
Author_Institution :
Coll. of Inf. Sci. & Technol., Northwest Univ., Xi´´an, China
Abstract :
A time-domain RS (Reed-Solomon) encoder was studied in this paper. Firstly analyzed coding theory of RS codes under the finite field, and focuses on the implementations of constant coefficients parallel multiplier under regular basis. On this basis, designed the encoder of RS (255,223) symmetrical structure in the Quartus7.0 build environment using the symmetry of polynomial coefficients, and use Matlab to prepare RS encoder debug and procedures verification, finally, obtained simulation results with the ModelSim5.8. The results show that the encoder is in good condition, and speed and occupancy characteristics of the hardware resources are limited compared with the existing type design.
Keywords :
Reed-Solomon codes; electronic engineering computing; field programmable gate arrays; logic design; mathematics computing; FPGA; Matlab; ModelSim 5.8; Quartus7.0 build environment; RS encoder debug; RS encoder design; RS symmetrical structure; coding theory; constant coefficients parallel multiplier; polynomial coefficients; procedures verification; time domain Reed-Solomon encoder; Educational institutions; Electronic mail; Error correction codes; Field programmable gate arrays; Galois fields; Information science; Mobile communication; Reed-Solomon codes; Space technology; Time domain analysis; FPGA; Reed-Solomon codes; encoder;
Conference_Titel :
Advanced Computer Control (ICACC), 2010 2nd International Conference on
Conference_Location :
Shenyang
Print_ISBN :
978-1-4244-5845-5
DOI :
10.1109/ICACC.2010.5486970
