BIST architectures selection based on behavioral testing

Author

Biasoli, G. ; Ferrandi, F. ; Fin, A. ; Fummi, F. ; Sciuto, D.

Author_Institution

Dipartimento di Elettronica, Politecnico di Milano, Italy

fYear

2000

fDate

2000

Firstpage

292

Lastpage

298

Abstract

BIST techniques have been widely explored to create the best performing self-testing architecture. Their success depends on the type of test pattern required by the circuit under test. The main goal of the paper is to show a methodology, based on behavioral information, to identify the best suited BIST architecture for a given circuit under test. LFSR-based architectures for behavioral test sequences, providing a high stuck-at fault coverage, have been explored and evaluated

Keywords

VLSI; built-in self test; circuit CAD; design for testability; integrated circuit testing; logic CAD; logic testing; sequences; shift registers; BIST architectures selection; DFT; LFSR-based architectures; VHDL descriptions; behavioral test sequences; behavioral testing; compact test sequences identification; high stuck-at fault coverage; linear feedback shift registers; self-testing architecture; test pattern; Automatic testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Clocks; Costs; Fault detection; Performance analysis; Performance evaluation;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Conference_Location

Yamanashi

ISSN

1550-5774

Print_ISBN

0-7695-0719-0

Type

conf

DOI

10.1109/DFTVS.2000.887169

Filename

887169