Title :
Testing the configurability of dynamic FPGAs
Author :
Park, N. ; Ruiwale, S.J. ; Lombardi, F.
Author_Institution :
Dept. of Comput. Sci., Oklahoma State Univ., Stillwater, OK, USA
Abstract :
This paper addresses configurability testing of dynamic FPGAs, i.e. the process to test the state configuration of the FPGA through specific functions which permits one to establish controllability and observability (by read and write operations). Configurability is accomplished in a dynamic FPGA by using a dedicated CPU interface. The CPU interface is characterized by different functional modules (mainly at register level) to permit state access; this is achieved using mapping, masking and addressing functions, and is tested for stuck-at and bridging faults in the bits of the Map and Mask Registers. The proposed approach for configurability testing has been evaluated on the XC6216 FPGA
Keywords :
VLSI; controllability; field programmable gate arrays; integrated circuit testing; logic testing; observability; XC6216 FPGA; addressing functions; bridging faults; configurability testing; controllability; dedicated CPU interface; dynamic FPGA; dynamically reconfigurable FPGAs; map register; mapping functions; mask register; masking functions; observability; state access; state configuration; stuck-at faults; Circuit faults; Circuit testing; Controllability; Field programmable gate arrays; Logic testing; Observability; Programmable logic arrays; Programmable logic devices; Reconfigurable logic; Registers;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.887171
