Analysis of surface and substrate deep-trap effects on gate-lag phenomena in GaAs MESFETs

The gate-lag in GaAs MESFETs is a phenomenon that the drain current shows slow transient when the gate voltage is changed abruptly. This is a serious problem in both digital and analog GaAs ICs, but its mechanism is not well clarified. The surface states are thought to be main causes of this phenomenon, and device structures which can reduce surface-state effects, such as a self-aligned structure and a recessed-gate structure, are adopted. But the gate-lag sometimes arises even in these structures. So, in this work, we have studied the gate-lag phenomena in these device structures by two-dimensional numerical simulation, and found that the gate-lag may not be completely suppressed in the recessed-gate structure. In addition, we have simulated the substrate deep-trap effects, and found that abnormal transient can arise when the off-state gate voltage is deeply negative