• DocumentCode
    267709
  • Title

    Day 2: Mini-tutorial: Challenges to the design and optimization of cyber-physical systems

  • Author

    Zebo Peng

  • Author_Institution
    Embedded Syst. Lab., Linkoping Univ., Linkoping, Sweden
  • fYear
    2014
  • fDate
    16-18 Dec. 2014
  • Abstract
    Summary form only given. We are witnessing an exponential increase of cyber-physical systems where the computational components interact with the physical world in a tightly manner. More and more of these systems are nowadays used for safety-critical applications, such as automotive electronics and medical equipment. These safety-critical applications impose stringent requirements on reliability, efficiency, low-power and testability of the underlying VLSI hardware implementation. With silicon technology scaling, however, VLSI circuits is built with smaller transistors, perform at higher clock frequencies, run at lower voltage levels, and operate very often at higher temperature. All these have major negative impact on reliability, performance, power-efficiency and testability. We are therefore facing the challenges of how to address all these technical problems and their interplay with the stringent real-time requirements imposed by many safety-critical applications. This talk will discuss the design of such cyber-physical systems by considering both fault-tolerance and real-time requirements at the same time. It will describe several key challenges and some emerging solutions to the design and optimization of such systems. In particular, it will present time-redundancy based fault-tolerance techniques to address transient faults which have become more and more common in nano-scale technology. It will also describe several design tradeoffs including hardware/software co-design solutions for the optimization of cyber-physical systems.
  • Keywords
    fault tolerant computing; hardware-software codesign; VLSI circuits; VLSI hardware implementation; clock frequency; cyber-physical system design; cyber-physical system optimization; efficiency requirement; hardware-software codesign; low-power requirement; nanoscale technology; reliability requirement; safety-critical applications; silicon technology scaling; testability requirement; time-redundancy based fault-tolerance techniques; transient faults; transistors; very large scale integration; Fault tolerance; Hardware; Integrated circuit reliability; Optimization; Real-time systems; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Test Symposium (IDT), 2014 9th International
  • Conference_Location
    Algiers
  • Type

    conf

  • DOI
    10.1109/IDT.2014.7038574
  • Filename
    7038574