DocumentCode
267714
Title
Design, manufacturing & test of integrated circuits in the nanotechnology era
Author
Kebichi, Omar
Author_Institution
ChipTest Estimate, Lexington, MA, USA
fYear
2014
fDate
16-18 Dec. 2014
Firstpage
13
Lastpage
17
Abstract
This article is meant to highlight the state of the art of chip design, manufacturing and test and the challenges it is facing while keeping up with Moore´s law at the nanoscale technology node. We will outline the different challenges the semiconductor industry is facing at sub-45 nm and highlight the different approaches the engineering community is adopting in the design, manufacturing and test fields.
Keywords
integrated circuit design; integrated circuit manufacture; integrated circuit testing; nanotechnology; semiconductor industry; Moore´s law; chip design; engineering community; integrated circuit design; integrated circuit manufacturing; integrated circuit testing; nanoscale technology node; semiconductor industry; Built-in self-test; Chip scale packaging; Lithography; Logic gates; Random access memory; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (IDT), 2014 9th International
Conference_Location
Algiers
Type
conf
DOI
10.1109/IDT.2014.7038579
Filename
7038579
Link To Document