A new efficient reduction scheme to implement tree multipliers on FPGAs

Fast multipliers are essential for many applications such as digital signal processing (DSP) and image and video processing. Tree parallel multipliers are the fastest ones. The only disadvantage of tree multipliers over serial multipliers is its high cost in terms of area and power dissipation. In this paper, we present a new efficient reduction scheme to implement tree multipliers on field programmable gate arrays (FPGAs) in a way that is more suitable for the lookup tables (LUTs) structure in FPGAs. The scheme is based on using a library of m.n counters. The aim of this scheme is to minimize the number of reduction steps to maximize reduction ratio which in turn reduces area and delay. A script was written to automate Verilog code generation according to the proposed scheme. Simulation and synthesis were conducted using Xilinx ISE suite. Results show that our scheme needs 13.4% and 32.6% less LUTs than the well-known Dadda and Wallace reduction tree schemes, respectively. Also, the delay is less by 44.8% and 52.8% than Dadda and Wallace schemes, respectively.