Design of a 10-bit, 50MSPS pipeline CMOS ADC

Based on the principle of Pipeline ADC, a 10-bit, 50-MS/s pipeline A/D converter is presented in this paper. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. This ADC is optimized for high static and dynamic performance applications in imaging and digital communications. It operates at 1.2 V power supply and achieves a power dissipation of 36 mW at typical case. The simulation results show that this ADC achieves over 56dB spurious-free dynamic range (SFDR) and 54DB SINAD. The prototype design is of a 10-bit pipeline ADC is fabricated in 0.13 μm CMOS standard mixed-signal process, and the IP core occupies an area of 0.52mm².