Title :
Prediction of fractional-N spurs for UHF PLL frequency synthesizers
Author :
Butterfield, D. ; Sun, B.
Author_Institution :
Qualcomm Inc., San Diego, CA, USA
Abstract :
Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to fractional-N divider techniques for PLL synthesizers. We analyze discrete "beat-note" spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods. The results are compared with measurements.
Keywords :
UHF circuits; UHF integrated circuits; digital integrated circuits; frequency synthesizers; phase locked loops; phase noise; radio equipment; UHF PLL frequency synthesizers; accumulator methods; discrete beat-note spurious levels; fast settling-time; fractional-N divider techniques; fractional-N spurs prediction; low phase noise; measurements; narrow channel spacing; portable wireless applications; Bandwidth; Channel spacing; Frequency conversion; Frequency synthesizers; Oscillators; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Signal analysis;
Conference_Titel :
Technologies for Wireless Applications, 1999. Digest. 1999 IEEE MTT-S Symposium on
Conference_Location :
Vancouver, BC, Canada
Print_ISBN :
0-7803-5152-5
DOI :
10.1109/MTTTWA.1999.755124
