Title :
Power reduction in energy recovery and square-wave clock distribution networks operating at half frequency with dual-edge triggered flip-flops
Author :
Esmaeili, S.E. ; Cowan, G.E.R. ; Al-Khalili, A.J.
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC
Abstract :
Dual-edge triggered flip-flops allow the operation of the clock distribution network at half the frequency leading to significant power reduction. We have simulated an energy recovery and a square-wave clock distribution network with 10,240 single-and dual-edge triggered flip-flops at 500 MHz and 250 MHz, respectively. Dual-edge triggering results in a total power reduction of 26% in the energy recovery clock. In square-wave clock distribution network, dual-edge triggering results in a total power reduction of 16%.
Keywords :
clocks; flip-flops; low-power electronics; dual-edge triggered flip-flops; dual-edge triggering; energy recovery clock; frequency 250 MHz; frequency 500 MHz; power reduction; square-wave clock distribution networks; Capacitance; Circuit simulation; Clocks; Computational modeling; Digital integrated circuits; Energy consumption; Flip-flops; Frequency estimation; Inverters; Testing;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2331-6
Electronic_ISBN :
978-1-4244-2332-3
DOI :
10.1109/NEWCAS.2008.4606337
