On the methodologies for VLSI yield enhancement (non-referred)

The profitability and success of semiconductor industry depends on the yield and reliability of VLSI circuits. Since the yield reflects the manufacturing cost directly, it is highly desired to evaluate the yield of a VLSI system precisely in the design stage. Moore´s law states that the density of ICs roughly doubles every two years. New breakthroughs in semiconductor design and manufacturing are likely to uphold this trend for at least one more decade. Shrinking geometries, lower power voltages, and higher frequencies have a negative impact on reliability. The failure of a single component may result in the failure of the entire system. If the individual component that caused the failure cannot be identified and replaced, then the entire system must be replaced. The cost of a reliability failure can therefore be significantly greater than the cost of the individual integrated circuit or circuits that caused the failure. In this paper we address the problems that cause the yield loss and identify the most effective techniques used in semiconductor industry to achieve better yield and reliability. Among the others, DFY and DFR have received our special attention. These new yield and reliability enhancement concepts have proven the effectiveness in yield and reliability improvement.