65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

The software-defined radio (SDR) concept aims at designing a re-configurable radio architecture accepting all cellular or non-cellular standards working in the 0-5 GHz frequency range. Some technical challenges have to be solved in order to address this concept. A fully digital SDR system implying an A/D conversion close to the antenna is not feasible in the case of mobile terminal. This paper presents the design of an analog processor which process RF signal in order to elect and convert into digital only the desired RF signal envelope. It uses the principle of a fast Fourier transform (FFT) to carry out basic analog functions with high accuracy at a low power consumption. Schematic and post layout simulations are exhibited. Estimated die area and power consumption are numbered.