Very high throughput iterative threshold decoder for convolutional self-doubly orthogonal codes

In this paper, we propose new circuit architectures dedicated for throughput improvement of iterative threshold decoder for the convolutional self-doubly orthogonal codes. A new pipeline strategy for the iterative threshold decoder is proposed which allows breaking down the critical path and then decreasing the processing delay. This proposed pipelining approach is based on a retiming technique. Consequently, an improvement in the throughput (4.56 times faster) of the decoder which could reach now 192.86 MHz is obtained at the cost of a very small increase in complexity (6.05 %).