DocumentCode :
2679761
Title :
Verification of fixed-point circuits specified by Taylor Series using Arithmetic Transform
Author :
Pang, Yu ; Radeck, Katarzyna ; Zilic, Zeljko
Author_Institution :
Dept. of Electr. & Comput. Eng., Mcgill Univ., Montreal, QC
fYear :
2008
fDate :
22-25 June 2008
Firstpage :
261
Lastpage :
264
Abstract :
For imprecise circuits, error is unavoidable, so implementations only realize specifications to some extent. Investigation of their difference is necessary. To overcome disadvantages of simulation, intermediate Arithmetic Transform polynomials are used as an analytical apparatus suitable to precision analysis for both the quantization (bit-width) and approximation sources, and a simple algorithm is proposed to compute each different type error and check an existing implementation of Taylor Series or real-valued polynomials whether satisfying the given error bound.
Keywords :
approximation theory; fixed point arithmetic; logic design; polynomials; quantisation (signal); Taylor series; approximation sources; fixed-point circuits; intermediate arithmetic transform polynomials; quantization; real-valued polynomials; type error; Algorithm design and analysis; Analytical models; Circuit simulation; Computational modeling; Design optimization; Field programmable gate arrays; Fixed-point arithmetic; Polynomials; Signal processing algorithms; Taylor series;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2331-6
Electronic_ISBN :
978-1-4244-2332-3
Type :
conf
DOI :
10.1109/NEWCAS.2008.4606371
Filename :
4606371
Link To Document :
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