Title :
Timing-driven Steiner tree construction for three-dimensional ICs
Author :
Yan, Jin-Tai ; Chen, Zhi-Wei ; Hu, Dun-Hao
Author_Institution :
Dept. of Comput. Sci. & Inf., Chung-Hua Univ., Hsinchu
Abstract :
Given a set of connecting nodes in a signal net on different layers for 3D ICs, based on the concept of hidden Steiner-point assignment on the same layer or different layers, a merging-based approach is proposed to construct a timing-driven 3D rectilinear Steiner tree. Compared with a spanning-tree-based approach, the experimental results show that our proposed approach has 9.7%~16% improvement in timing delay for the tested examples in reasonable CPU time.
Keywords :
integrated circuit design; integrated circuit interconnections; trees (mathematics); hidden Steiner-point assignment; three- dimensional IC; timing delay; timing-driven 3D rectilinear Steiner tree; timing-driven Steiner tree construction; Algorithm design and analysis; Computer science; Delay effects; Integrated circuit interconnections; Joining processes; Routing; Signal design; Steiner trees; Testing; Timing;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2331-6
Electronic_ISBN :
978-1-4244-2332-3
DOI :
10.1109/NEWCAS.2008.4606389
