Title :
Using SOI double-gate MOSFET NDR structures to improve ultra-low power full adder performance
Author :
Hassoune, I. ; Yang, X. ; O´Connor, I. ; Navarro, D.
Author_Institution :
Lyon Inst. of Nanotechnol., Lyon Univ., Ecully
Abstract :
In this paper, we propose a new efficient design of a hybrid full adder cell combining two logic styles and a negative differential resistance (NDR) device realized in a fully depleted (FD) silicon on insulator (SOI) double-gate (DG) MOSFET technology. Simulation results show significant (65%) power savings for asymmetric gate workfunction and independent gate control full adders with respect to standard CMOS circuits, with lower device count and comparable delay figures.
Keywords :
CMOS digital integrated circuits; MOSFET; adders; low-power electronics; silicon-on-insulator; SOI double-gate MOSFET NDR structure; asymmetric gate workfunction; fully depleted silicon on insulator; negative differential resistance; standard CMOS circuit; ultra-low power full adder design; Adders; CMOS logic circuits; CMOS technology; Circuit simulation; Delay; Logic design; Logic devices; MOSFET circuits; Power MOSFET; Silicon on insulator technology;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2331-6
Electronic_ISBN :
978-1-4244-2332-3
DOI :
10.1109/NEWCAS.2008.4606392
