Title :
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Author :
Jung, Moongon ; Liu, Xi ; Sitaraman, Suresh K. ; Pan, David Z. ; Lim, Sung Kyu
Author_Institution :
Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact of TSV placement in conjunction with various associated structures such as landing pad and dielectric liner on TSV interfacial crack. Next, we present a full-chip TSV interfacial crack analysis methodology based on design of experiments (DOE) and response surface method (RSM). Finally, we propose a design optimization methodology to mitigate the mechanical reliability problems in 3D ICs.
Keywords :
circuit optimisation; design of experiments; response surface methodology; three-dimensional integrated circuits; 3D IC optimization; TSV interfacial crack problem; TSV-induced thermomechanical stress; design of experiment; design optimization methodology; dielectric liner; dielectric liner interface; full-chip TSV interfacial crack analysis methodology; full-chip through-silicon-via interfacial crack analysis; mechanical reliability problem; response surface method; Silicon; Stress; Surface cracks; Three dimensional displays; Through-silicon vias; US Department of Energy;
Conference_Titel :
Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-1399-6
Electronic_ISBN :
1092-3152
DOI :
10.1109/ICCAD.2011.6105386