• DocumentCode
    2680726
  • Title

    Low-power multiple-bit upset tolerant memory optimization

  • Author

    Kim, Seokjoong ; Guthaus, Matthew R.

  • Author_Institution
    Dept. of CE, Univ. of California Santa Cruz, Santa Cruz, CA, USA
  • fYear
    2011
  • fDate
    7-10 Nov. 2011
  • Firstpage
    577
  • Lastpage
    581
  • Abstract
    In this paper, we propose a framework for analyzing Soft Error Rates (SER) including Multiple-Bit Upsets (MBU). Then, using this framework, we optimize the soft error tolerant voltage (Vtol) and interleaving distance (ID) of low-power, error-tolerant memories. Experimental results show that the total power can be reduced by an average of 30.5% with Vtol optimization and an average of 40.9% by simultaneously considering Vtol and ID together when compared to worst-case design practices.
  • Keywords
    Monte Carlo methods; radiation hardening (electronics); Monte Carlo; SER; error-tolerant memories; interleaving distance; low-power multiple-bit upset tolerant memory optimization; mobile embedded systems; multiple-bit upsets; soft error rates; soft error tolerant voltage; worst-case design practices; Arrays; Error analysis; Error correction codes; Optimization; Power demand; Random access memory; Transient analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4577-1399-6
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2011.6105388
  • Filename
    6105388
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2680726