• DocumentCode
    268082
  • Title

    Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs

  • Author

    Dubois, Fabien ; Sheibanyrad, Abbas ; Pétrot, Frédéric ; Bahmani, Maryam

  • Author_Institution
    TIMA Lab., UJF, Grenoble, France
  • Volume
    62
  • Issue
    3
  • fYear
    2013
  • fDate
    Mar-13
  • Firstpage
    609
  • Lastpage
    615
  • Abstract
    In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases.
  • Keywords
    distributed algorithms; network-on-chip; topology; 3D topologies; TSV-based 3D integration; blockage free; deadlock free; deadlock-free distributed routing algorithm; interconnect backbone; livelock free; low implementation cost distributed deterministic routing; planar topologies; through-silicon-vias; vertically partially connected 3D-NoC; vertically partially connected regular 2D topologies; virtual channels; Elevators; Integrated circuit interconnections; Network topology; Routing; System recovery; Three dimensional displays; Topology; Keywords—3D Integration; deadlock freedom; network-on-chip (NoC); routing algorithm;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2011.239
  • Filename
    6109239