DocumentCode :
268083
Title :
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks
Author :
Cuesta, Blas ; Ros, Alberto ; Gómez, M.E. ; Robles, Antonio ; Duato, Jose
Author_Institution :
Intel Labs. Barcelona, Barcelona, Spain
Volume :
62
Issue :
3
fYear :
2013
fDate :
Mar-13
Firstpage :
482
Lastpage :
495
Abstract :
A key aspect in the design of efficient multiprocessor systems is the cache coherence protocol. Although directory-based protocols constitute the most scalable approach, the limited size of the directory caches together with the growing size of systems may cause frequent evictions and, consequently, the invalidation of cached blocks, which jeopardizes system performance. Directory caches keep track of every memory block stored in processor caches in order to provide coherent access to the shared memory. However, a significant fraction of the cached memory blocks do not require coherence maintenance (even in parallel applications) because they are either accessed by just one processor or they are never modified. In this paper, we propose to deactivate the coherence protocol for those blocks that do not require coherence. This deactivation means directory caches do not have to keep track of noncoherent blocks, which reduces directory cache occupancy and increases its effectiveness. Since the detection of noncoherent blocks is carried out by the operating system, our proposal only requires minor hardware modifications. Simulation results show that, thanks to our proposal, directory caches can avoid the tracking of about 66 percent (on average) of the blocks accessed by a wide range of applications, thereby improving the efficiency of directory caches. This contributes either to shortening the runtime of parallel applications by 15 percent (on average) while keeping directory cache size or to maintaining performance while using directory caches 16 times smaller.
Keywords :
cache storage; operating systems (computers); parallel processing; performance evaluation; protocols; shared memory systems; directory cache efficiency improvement; directory cache occupancy reduction; directory cache size; directory-based cache coherence protocol; hardware modifications; multiprocessor systems; noncoherent block detection; noncoherent memory block tracking; operating system; parallel applications runtime; performance maintenance; processor cached block invalidation; scalable approach; shared memory coherent access; Coherence; Hardware; Maintenance engineering; Memory management; Proposals; Protocols; Strontium; Multiprocessor; cache coherence; coherence deactivation; directory cache; noncoherent blocks; operating system;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2011.241
Filename :
6109241
Link To Document :
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