DocumentCode
2680867
Title
Theory and VLSI implementation of multilevel median filters
Author
Arce, Gonzalo R. ; Warter, Peter J. ; Foster, Russell E.
Author_Institution
Dept. of Electr. Eng., Delaware Univ., Newark, DE, USA
fYear
1988
fDate
7-9 June 1988
Firstpage
2795
Abstract
The properties of multilevel median filters are summarized, and a detailed analysis of their efficient implementation is given. In particular, a bit-serial compare/exchange module is described. This module is then used as the building block of a systolic array for the efficient implementation of these two-dimensional filtering algorithms. The architecture described yields a low area complexity, which allows a single chip VLSI implementation.<>
Keywords
VLSI; digital filters; VLSI implementation; bit-serial compare/exchange module; building block; low area complexity; multilevel median filters; two-dimensional filtering algorithms; Additive noise; Additive white noise; Filtering theory; Matched filters; Noise level; Recursive estimation; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location
Espoo, Finland
Type
conf
DOI
10.1109/ISCAS.1988.15519
Filename
15519
Link To Document